Author of the publication

Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller.

, , and . NORCAS, page 1-6. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style., , , , , , , , and . DAC, page 873-878. ACM Press, (1999)A formal, model-driven design flow for system simulation and multi-core implementation., , , , , and . SIES, page 254-263. IEEE, (2015)System Design for DSP Applications Using the MASIC Methodology., , and . DATE, page 630-635. IEEE Computer Society, (2004)Competence Networks in the Era of CPS - Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center., , , , , , , , , and 1 other author(s). CyPhy/WESE, volume 11971 of Lecture Notes in Computer Science, page 264-283. Springer, (2019)Specification of Exception Handling in Grammar-Based Hardware Synthesis., , and . EUROMICRO, page 10038-10041. IEEE Computer Society, (1998)From Simulink to NoC-based MPSoC on FPGA., and . DATE, page 1-4. European Design and Automation Association, (2014)Grammar-based design of embedded systems., , , , and . J. Syst. Archit., 47 (3-4): 225-240 (2001)Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller., , and . NORCAS, page 1-6. IEEE, (2017)Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs., , and . NORCAS, page 1-6. IEEE, (2017)Artificial neural network emulation on NOC based multi-core FPGA platform., , and . NORCHIP, page 1-4. IEEE, (2012)