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Dual-Vdd Buffer Insertion for Power Reduction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1498-1502 (2008)Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming., , , and . ACM Trans. Design Autom. Electr. Syst., 13 (2): 30:1-30:29 (2008)Minimal skew clock embedding considering time variant temperature gradient., , , and . ISPD, page 173-180. ACM, (2007)Enterprise Human Resources Information Mining Based on Improved Apriori Algorithm., and . J. Networks, 8 (5): 1138-1145 (2013)Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 24-33 (2013)Piecewise linear model for transmission line with capacitive loading and ramp input., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 928-937 (2005)Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 734-738 (2007)Quasi-orthogonal space-time block coded transceiver systems over frequency selective wireless fading channels., and . ICASSP (2), page 321-324. IEEE, (2004)Interconnect design for deep submicron ICs., , , , and . ICCAD, page 478-485. IEEE Computer Society / ACM, (1997)Performance optimization of VLSI interconnect layout., , , and . Integr., 21 (1-2): 1-94 (1996)