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Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.

, , , , , , and . IACR Cryptol. ePrint Arch., (2019)

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SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment., , , , , , , and . VTS, page 1-6. IEEE, (2020)FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection., , , , , , , and . HOST, page 81-90. IEEE, (2019)RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level., , , , , and . VTS, page 1-6. IEEE, (2019)Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (4): 29:1-29:27 (2021)Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation., , , , and . ACM Trans. Design Autom. Electr. Syst., 25 (4): 35:1-35:22 (2020)Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design., , , , , , and . IACR Cryptol. ePrint Arch., (2019)Security Rule Checking in IC Design., , and . Computer, 49 (8): 54-61 (2016)A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2152-2165 (2020)SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 25 (3): 26:1-26:27 (2020)Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1003-1016 (2019)