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Disambiguation of "Plíva, Jan"

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Offset-Compensation Systems for Multi-Gbit/s Optical Receivers.

, , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 235-255. Springer, (2019)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tsai-Yu Jansen

Einfluss der Konversion laparoskopischer Operationen auf Tumorwachstum, hepatische Metastasierung und Tumorangiogenese. Uni Heidelberg, (2010)

Dirk Jansen

Temperaturkorrektur von mit dem Falling-Weight-Deflectometer gemessenen Deflexionen auf Asphaltbefestigungen. Uni Duisburg-Essen, (2009)

Matthäus Janczyk

Synthese funktionalisierter Trinukleotide und ihre Anwendung bei der Randomisierung. Uni Greifswald, (2009)

Christoph Janello

Wertschöpfung im digitalisierten Buchmarkt. Uni München, (2010)

Richard Janissen

Biomolecular based nano-manipulation with a combined atomic force microscope and single molecule fluorescence setup. Uni Düsseldorf, (2009)
 

Other publications of authors with the same name

A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (3): 845-855 (2019)4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2018)A Low-Power Fast Settling 5.4 - 8.4 GHz Digitally Controlled Oscillator in 45 nm RFSOI CMOS., , , , and . MWSCAS, page 113-116. IEEE, (2020)A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends., , , and . VLSI-SoC, page 46-51. IEEE, (2019)Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (3): 636-648 (2016)Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS., , , , and . SoCC, page 253-257. IEEE, (2017)A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment., , , and . SoCC, page 278-283. IEEE, (2019)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)Decompressors using nonlinear codes., , and . Microprocess. Microsystems, (2020)Offset-Compensation Systems for Multi-Gbit/s Optical Receivers., , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 235-255. Springer, (2019)