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Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.

J. Ambrosi, A. Ankit, R. Antunes, S. Chalamalasetti, S. Chatterjee, I. Hajj, G. Fachini, P. Faraboschi, M. Foltin, S. Huang, W. Hwu, G. Knuppe, S. Lakshminarasimha, D. Milojicic, M. Parthasarathy, F. Ribeiro, L. Rosa, K. Roy, P. Silveira, and J. Strachan. ICRC, page 1-13. IEEE, (2018)

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Georg Foltin

Ulrich Foltin

Oliver Foltin

Thomas Foltin

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Knowledge Graph Empowered Machine Learning Pipelines for Improved Efficiency, Reusability, and Explainability.R. Venkataramanan, A. Tripathy, M. Foltin, H. Yip, A. Justine, and A. Sheth. IEEE Internet Comput., 27 (1): 81-88 (January 2023)Towards Rapid Autonomous Electron Microscopy with Active Meta-Learning.G. Saranathan, M. Foltin, A. Tripathy, M. Ziatdinov, A. Koomthanam, S. Bhattacharya, A. Ghosh, K. Roccapriore, S. Sukumar, and P. Faraboschi. SC Workshops, page 81-87. ACM, (2023)PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.A. Ankit, I. Hajj, S. Chalamalasetti, S. Agarwal, M. Marinella, M. Foltin, J. Strachan, D. Milojicic, W. Hwu, and K. Roy. IEEE Trans. Computers, 69 (8): 1128-1142 (2020)Data-Aware Storage Tiering for Deep Learning.C. Xu, S. Bhattacharya, M. Foltin, S. Byna, and P. Faraboschi. PDSW@SC, page 23-28. IEEE, (2021)Regular Expression Matching with Memristor TCAMs for Network Security.C. Graves, W. Ma, X. Sheng, B. Buchanan, L. Zheng, S. Lam, X. Li, S. Chalamalasetti, L. Kiyama, M. Foltin and 2 other author(s). NANOARCH, page 65-71. ACM, (2018)X-TIME: An in-memory engine for accelerating machine learning on tabular data with CAMs.G. Pedretti, J. Moon, P. Bruel, S. Serebryakov, R. Roth, L. Buonanno, T. Ziegler, C. Xu, M. Foltin, P. Faraboschi and 2 other author(s). CoRR, (2023)Workflows Community Summit 2022: A Roadmap Revolution.R. da Silva, R. Badia, V. Bala, D. Bard, P. Bremer, I. Buckley, S. Caíno-Lores, K. Chard, C. Goble, S. Jha and 41 other author(s). CoRR, (2023)Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.M. Foltin, B. Foutz, and S. Tyler. DAC, page 158-163. ACM, (2002)PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.A. Ankit, I. Hajj, S. Chalamalasetti, G. Ndu, M. Foltin, R. Williams, P. Faraboschi, W. mei W. Hwu, J. Strachan, K. Roy and 1 other author(s). ASPLOS, page 715-731. ACM, (2019)FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator.M. Foltin, G. Aguiar, R. Antunes, P. Silveira, G. Knuppe, J. Ambrosi, S. Chatterjee, J. Kolhe, S. Lakshiminarashimha, D. Milojicic and 10 other author(s). ICRC, page 44-53. IEEE, (2019)

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Disambiguation of "Foltin, Martin"

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Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.

Please choose a person to relate this publication to

Georg Foltin

Georg Foltin

Ulrich Foltin

Oliver Foltin

Thomas Foltin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Foltin, Martin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.

Please choose a person to relate this publication to

Georg Foltin

Georg Foltin

Ulrich Foltin

Oliver Foltin

Thomas Foltin

Other publications of authors with the same name

Disambiguation

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Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.