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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.

, и . FPGA, стр. 187. ACM, (2019)

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Jiafeng Zhang

Jian Xie

Yangpei Xie

Zhenwei Xie

Mingliang Xie

 

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Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method., , и . ISCAS, стр. 1-5. IEEE, (2019)Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing., , и . ISCAS, стр. 89-92. IEEE, (2012)Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform., , и . FPGA, стр. 156. ACM, (2022)Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography., , , и . CODES+ISSS, стр. 5-6. IEEE, (2022)FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision., , , , и . IJCKG, стр. 45-53. ACM, (2021)Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets., , , , и . CCKS, том 1466 из Communications in Computer and Information Science, стр. 315-320. Springer, (2021)AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC., , , и . ICFPT, стр. 6. IEEE, (2023)Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy., и . ISQED, стр. 1-8. IEEE, (2023)Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity., и . FPGA, стр. 187. ACM, (2019)Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography., , , и . IEEE Trans. Emerg. Top. Comput., 10 (2): 1222-1228 (2022)