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On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.

, , and . DATE, page 616-621. ACM, (2008)

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An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect., , , and . VLSI Design, page 583-588. IEEE Computer Society, (2007)Special session 12C: Young professionals in test - Town meeting., , and . VTS, page 1. IEEE Computer Society, (2014)A Built-in Test and Characterization Method for Circuit Marginality Related Failures., and . ISQED, page 838-843. IEEE Computer Society, (2008)On Accelerating Soft-Error Detection by Targeted Pattern Generation., , and . ISQED, page 723-728. IEEE Computer Society, (2007)Special session 11C: Young professionals in test - Elevator talks., and . VTS, page 1. IEEE Computer Society, (2014)A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays., , and . IEEE Trans. Computers, 61 (7): 986-998 (2012)A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits., , and . ACM Great Lakes Symposium on VLSI, page 529-534. ACM, (2009)On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits., , and . DATE, page 616-621. ACM, (2008)DFM-aware fault model and ATPG for intra-cell and inter-cell defects., , , , and . ITC, page 1-10. IEEE, (2017)Dynamic power minimization during combinational circuit testing as a traveling salesman problem., , , and . Congress on Evolutionary Computation, page 1088-1095. IEEE, (2005)