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Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown.

, , , , and . DDECS, page 12-15. IEEE, (2012)

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Reliability enhancement via Sleep Transistors., , and . LATW, page 1-6. IEEE, (2011)Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown, , , , and . SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design, page 1--6. New York, NY, USA, ACM, (2009)Verlustleistungsreduzierung bei dynamischen TSPC-Schaltungstechniken., , , and . GI Jahrestagung (1), volume P-67 of LNI, page 450. GI, (2005)