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Area optimization for leakage reduction and thermal stability in nanometer scale technologies.

, and . ASP-DAC, page 231-236. IEEE, (2006)

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The importance of including thermal effects in estimating the effectiveness of power reduction techniques., , and . CICC, page 301-304. IEEE, (2005)Variable latency caches for nanoscale processor., , , , and . SC, page 20. ACM Press, (2007)Thermal Management of On-Chip Caches Through Power Density Minimization., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 592-604 (2007)Power density minimization for highly-associative caches in embedded processors., , , and . ACM Great Lakes Symposium on VLSI, page 100-104. ACM, (2006)A self-adjusting clock tree architecture to cope with temperature variations., , , and . ICCAD, page 75-82. IEEE Computer Society, (2007)Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 15 (8): 963-970 (2007)Attaining Thermal Integrity in Nanometer Chips., and . ISCAS, page 3223-3226. IEEE, (2007)Thermal Management of On-Chip Caches Through Power Density Minimization., , , and . MICRO, page 283-293. IEEE Computer Society, (2005)A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay., and . ISCAS, page 3736-3739. IEEE, (2007)On the Scaling of Temperature-Dependent Effects., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (10): 1882-1888 (2007)