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Disambiguation of "Khan, Omer"

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MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores.

, and . ICCD, page 97-104. IEEE, (2022)

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Emin Sinan Ömeroglu

Lutful Mannan Osama Omer

Abrehet Mohammed Omer

Lutful Mannan Osama Omer

Osman Hussein Omer

 

Other publications of authors with the same name

IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks., and . CoRR, (2019)Toward Holistic Soft-Error-Resilient Shared-Memory Multicores., and . Computer, 46 (10): 56-64 (2013)Bilinear Map Based One-Time Signature Scheme with Secret Key Exposure., , , , and . IACR Cryptol. ePrint Arch., (2021)Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design., and . IEEE Trans. Emerg. Top. Comput., 7 (2): 242-243 (2019)Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale., , , and . ACM Trans. Archit. Code Optim., 16 (1): 4:1-4:27 (2019)Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors., and . IEEE Trans. Computers, 59 (5): 651-665 (2010)MARTHA: architecture for control and emulation of power electronics and smart grid systems., , , and . DATE, page 519-524. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An Efficient Algorithm for the Construction of Dynamically Updating Trajectory Networks., , and . HPEC, page 1-7. IEEE, (2021)Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs., , , , , and . HPCA, page 213-224. IEEE Computer Society, (2014)MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration., , , , and . ISPASS, page 145-156. IEEE, (2023)