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Disambiguation of "Jabir, Abusaleh M."

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Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability.

, , , and . IET Comput. Digit. Tech., 4 (5): 428-437 (2010)

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Jabir Mohsin Jabir

Nizar Jabir

Sarah Jabir

Jabir Shanshool

Shaikha Al-Jabir

 

Other publications of authors with the same name

BCH code based multiple bit error correction in finite field multiplier circuits., , , , and . ISQED, page 615-620. IEEE, (2011)VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases., , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 258-269. Springer, (2012)On the design of different concurrent EDC schemes for S-Box and GF(p)., , , , and . ISQED, page 211-218. IEEE, (2010)Learning method for ex-situ training of memristor crossbar based multi-layer neural network., , , and . ICUMT, page 305-310. IEEE, (2017)A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields., , , and . ECCTD, page 600-603. IEEE, (2011)A Galois Field Based Logic Synthesis Approach with Testability., , , , and . VLSI Design, page 629-634. IEEE Computer Society, (2008)Yield Estimation of a Memristive Sensor Array., , , , , , and . IOLTS, page 1-2. IEEE, (2020)A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations., , , and . IOLTS, page 1-4. IEEE, (2021)Analytic models for crossbar read operation., , , , and . IOLTS, page 3-4. IEEE, (2016)Parasitic effects on memristive logic architecture., , , and . PATMOS, page 1-5. IEEE, (2017)