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The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models., , , , , , , , , and 24 other author(s). CoRR, (2024)RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model., , , and . CoRR, (2023)RouteNet: routability prediction for mixed-size designs using convolutional neural network., , , , , , and . ICCAD, page 80. ACM, (2018)Robustify ML-Based Lithography Hotspot Detectors., , , , and . ICCAD, page 134:1-134:7. ACM, (2022)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization., , , and . CoRR, (2024)Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS., , , and . CoRR, (2024)The Dark Side: Security and Reliability Concerns in Machine Learning for EDA., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (4): 1171-1184 (April 2023)Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation., , , , , and . CoRR, (2020)SPA-Net: A Deep Learning Approach Enhanced Using a Span-Partial Structure and Attention Mechanism for Image Copy-Move Forgery Detection., , , , , and . Sensors, 23 (14): 6430 (July 2023)SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model., , , and . CoRR, (2024)