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Disambiguation of "Hsu, Ting-Shuo"

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An ISA-level Accurate Fault Simulator for System-level Fault Analysis.

, , , , , and . ATS, page 1-6. IEEE, (2020)

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Hsiao-Ting Hsu

Chun-Ting Hsu

Shu-Ting Hsu

Shuo Li

Shuo Liu

 

Other publications of authors with the same name

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2017)An ISA-level Accurate Fault Simulator for System-level Fault Analysis., , , , , and . ATS, page 1-6. IEEE, (2020)Design and analysis of a many-core processor architecture for multimedia applications., , , , and . APSIPA, page 1-6. IEEE, (2012)A Region-Based Framework for Design Feature Identification of Systematic Process Variations., , , and . Asian Test Symposium, page 265-270. IEEE Computer Society, (2013)Chip clustering with mutual information on multiple clock tests and its application to yield tuning., , , and . ICCD, page 243-248. IEEE Computer Society, (2014)Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data., , and . Asian Test Symposium, page 320-325. IEEE Computer Society, (2012)Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures., , , , , and . MES, page 41-44. ACM, (2013)NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators., , , , and . VLSI-DAT, page 1-4. IEEE, (2019)Design of a scalable many-core processor for embedded applications., , , , , and . ASP-DAC, page 24-25. IEEE, (2015)A fast and accurate network-on-chip timing simulator with a flit propagation model., , , and . ASP-DAC, page 797-802. IEEE, (2015)