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An architectural co-synthesis algorithm for energy-aware network-on-chip design.

, , , , and . SAC, page 680-684. ACM, (2007)

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Cache leakage control mechanism for hard real-time systems., , , and . CASES, page 248-256. ACM, (2007)HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction., and . ISLPED, page 114-119. ACM, (2004)Memory access aware power gating for MPSoCs., , , and . ASP-DAC, page 121-126. IEEE, (2012)Memory Latency Reduction via Thread Throttling., , , and . MICRO, page 53-64. IEEE Computer Society, (2010)Message from the general co-chairs., and . ISLPED, page 1. IEEE, (2017)Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs., , , and . RACS, page 430-436. ACM, (2015)The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper., , , , , , , , , and 2 other author(s). ICCAD, page 1-6. ACM, (2019)Thermal modeling for 3D-ICs with integrated microchannel cooling., , and . ICCAD, page 256-263. ACM, (2009)BioRoute: a network-flow based routing algorithm for digital microfluidic biochips., , and . ICCAD, page 752-757. IEEE Computer Society, (2007)A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads., , , and . ISCAS, page 1-5. IEEE, (2021)