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Disambiguation of "Kang, Sung-Mo"

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A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.

, , , , , and . ISCAS (2), page 781-784. IEEE, (2004)

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Koeng-Mo Sung

Sung-Mo Moon

Sung-Mo Ku

Koeng-Mo Sung

Sung-Goon Kang

 

Other publications of authors with the same name

Minimum delay optimization for domino circuits - a coupling-aware approach., , , and . ACM Trans. Design Autom. Electr. Syst., 8 (2): 202-213 (2003)VeriCDF: a new verification methodology for charged device failures., , and . DAC, page 874-879. ACM, (2002)Energy-efficient skewed static logic with dual Vt: design and synthesis., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 64-70 (2003)Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (7): 442-446 (2011)Distance-Based Cycle-Free Persistent Formation: Global Convergence and Experimental Test With a Group of Quadcopters., , and . IEEE Trans. Ind. Electron., 64 (1): 380-389 (2017)Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction., and . DAC, page 750-755. ACM, (2000)Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models., , , and . I. J. Circuit Theory and Applications, 19 (6): 579-592 (1991)Fast settling frequency synthesizer with two-point channel control paths., and . I. J. Circuit Theory and Applications, 40 (10): 1071-1083 (2012)3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance., , and . SoCC, page 1-6. IEEE, (2005)ILLIADS: a fast timing and reliability simulator for digital MOS circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (9): 1387-1402 (1993)