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A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM., and . NORCAS, page 1-6. IEEE, (2019)Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors., , , , and . CoRR, (2019)System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration., , , , , and . FPL, page 293-300. IEEE, (2019)Comprehensive curriculum for reconfigurable heterogeneous computer architecture education., , and . IET Circuits Devices Syst., 11 (4): 292-298 (2017)Multi-level memristive voltage divider: programming scheme trade-offs., , and . MEMSYS, page 259-268. ACM, (2018)Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures., , , , , and . IEEE Comput. Archit. Lett., 22 (1): 9-12 (January 2023)Autonomous Driving in the Curriculum of Computer Architecture., , , and . EWME, page 11-16. IEEE, (2018)Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing., , and . FAS*W@SASO/ICAC, page 68-69. IEEE, (2019)Direct state transfer in MLC based memristive ReRAM devices for ternary computing., and . ECCTD, page 1-5. IEEE, (2020)Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic., , and . ICECS, page 1-6. IEEE, (2021)