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Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)

, , , , and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2012)

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Advanced MRI reconstruction toolbox with accelerating on GPU., , , , , , , , and . Parallel Processing for Imaging Applications, volume 7872 of SPIE Proceedings, page 78720Q. SPIE, (2011)Checkpoint Repair for High-Performance Out-of-Order Execution Machines., and . IEEE Trans. Computers, 36 (12): 1496-1514 (1987)FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2032-2045 (2016)PyTorch-Direct: Enabling GPU Centric Data Access for Very Large Graph Neural Network Training with Irregular Accesses., , , , , , , and . CoRR, (2021)PIGEON: Optimizing CUDA Code Generator for End-to-End Training and Inference of Relational Graph Neural Networks., , , , , , and . CoRR, (2023)CODAG: Characterizing and Optimizing Decompression Algorithms for GPUs., , , , , , , , , and 3 other author(s). CoRR, (2023)Toward Application-Aware Security and Reliability., , , , , , and . IEEE Secur. Priv., 5 (1): 57-62 (2007)Incremental Compiler Transformations for Multiple Instruction Retry., , , and . Softw. Pract. Exp., 24 (12): 1179-1198 (1994)The superblock: An effective technique for VLIW and superscalar compilation., , , , , , , , , and 2 other author(s). J. Supercomput., 7 (1-2): 229-248 (1993)Adaptive Cache Bypass and Insertion for Many-core Accelerators., , , , , , and . MES, page 1-8. ACM, (2014)