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Disambiguation of "Cho, Sung-Gun"

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A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.

, , and . IEEE J. Solid State Circuits, 56 (2): 612-623 (2021)

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Sung-bok Cho

Gyu-Sung Cho

Sung-Jun Cho

Sung-Yong Cho

Sung-Hyun Cho

 

Other publications of authors with the same name

A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS., , and . VLSI Circuits, page 240-. IEEE, (2019)PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA., , , and . VLSI Circuits, page 1-2. IEEE, (2021)Concatenated BCH codes for NAND flash memories., and . ICC, page 2611-2616. IEEE, (2012)Error patterns in belief propagation decoding of polar codes and their mitigation methods., , and . ACSSC, page 1199-1203. IEEE, (2016)Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 59 (4): 1235-1245 (April 2024)A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture., , and . IEEE J. Solid State Circuits, 56 (2): 612-623 (2021)Block-Wise Concatenated BCH Codes for NAND Flash Memories., , , and . IEEE Trans. Commun., 62 (4): 1164-1177 (2014)A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS., , and . CICC, page 1-4. IEEE, (2019)Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes., , and . GLOBECOM, page 1-6. IEEE, (2017)A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS., , and . A-SSCC, page 233-236. IEEE, (2017)