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Exploiting reuse and vectorization in blocked stencil computations on CPUs and GPUs., , , , and . SC, page 52:1-52:44. ACM, (2019)Optimizing Data Movement and Achieving Performance Portability with Fine-Grained Data Blocking.. University of Utah, USA, (2022)Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-Iteration., , , , and . CoRR, (2022)SIMD code generation for stencils on brick decompositions., , , , and . PPoPP, page 423-424. ACM, (2018)Maximizing Performance Through Memory Hierarchy-Driven Data Layout Transformations., , , and . MCHPC@SC, page 1-10. IEEE, (2022)Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration., , , , and . ACM Trans. Archit. Code Optim., 20 (1): 16:1-16:26 (March 2023)Code Synthesis for Sparse Tensor Format Conversion and Optimization., , , , , , and . CGO, page 28-40. ACM, (2023)Performance Portability Evaluation of Blocked Stencil Computations on GPUs., , , , , , and . SC Workshops, page 1005-1018. ACM, (2023)Improving communication by optimizing on-node data movement with data layout., , , and . PPoPP, page 304-317. ACM, (2021)