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Disambiguation of "Han, Kwangsoo"

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Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products.

, , , and . ASP-DAC, page 697-704. IEEE, (2016)

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Kwangsoo Kwon

Kwangsoo Kim

Muxin Han

Luyang Han

Mei Han

 

Other publications of authors with the same name

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes., , , , , and . DAC, page 51:1-51:6. ACM, (2017)Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products., , , and . ASP-DAC, page 697-704. IEEE, (2016)A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions., , , and . SLIP@DAC, page 2:1-2:8. ACM, (2018)Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI., , , , , and . ICCAD, page 667-674. IEEE, (2017)Benchmarking of mask fracturing heuristics., , , , , and . ICCAD, page 246-253. IEEE, (2014)Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees., , , , , , and . ISPD, page 10-17. ACM, (2018)Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router., , and . DAC, page 68:1-68:6. ACM, (2015)Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes., , , and . ISQED, page 104-110. IEEE, (2017)A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction., , , , and . DAC, page 26:1-26:6. ACM, (2015)OCV-aware top-level clock tree optimization., , , , and . ACM Great Lakes Symposium on VLSI, page 33-38. ACM, (2014)