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Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.

B. Silveira, R. Ferreira, G. Paim, C. Diniz, and E. da Costa. NEWCAS, page 277-280. IEEE, (2017)

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Cláudio Walter

Cláudio Faria

Rogério Palhares Diniz

Roberto Antonio Costa Diniz

Carlos Alberto Diniz

Other publications of authors with the same name

Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder.B. Garcia, B. Silveira, C. Diniz, D. Palomino, and G. Corrêa. LASCAS, page 1-4. IEEE, (2023)High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation.D. Freitas, B. Nagai, M. Grellert, C. Diniz, and G. Corrêa. SBCCI, page 1-6. IEEE, (2022)Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding.B. Silveira, L. Neto, D. Palomino, C. Diniz, and G. Corrêa. ISCAS, page 1-5. IEEE, (2022)Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing.L. Gobatto, M. Saquetti, C. Diniz, B. Zatt, W. Cordeiro, and J. Azambuja. ISCAS, page 1813-1817. IEEE, (2022)Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform.M. Stigger, V. Lima, L. Soares, C. Diniz, and S. Bampi. LASCAS, page 1-4. IEEE, (2020)A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.C. Diniz, B. Zatt, L. Agostini, A. Susin, and S. Bampi. ICME, page 1138-1141. IEEE, (2009)Timing and interface communication analysis of H.264/AVC encoder using SystemC model.B. Zatt, C. Diniz, L. Agostini, and S. Bampi. VLSI-SoC, page 235-240. IEEE, (2010)A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder.T. da Silva, C. Diniz, J. Vortmann, L. Agostini, A. Susin, and S. Bampi. PSIVT, volume 4872 of Lecture Notes in Computer Science, page 5-15. Springer, (2007)A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding.L. Soares, C. Diniz, E. da Costa, and S. Bampi. SBCCI, page 1-6. IEEE, (2016)Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.C. Diniz, M. Fonseca, E. da Costa, and S. Bampi. NEWCAS, page 1-4. IEEE, (2015)

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Disambiguation of "Diniz, Cláudio Machado"

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Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.

Please choose a person to relate this publication to

Cláudio Walter

Cláudio Faria

Rogério Palhares Diniz

Roberto Antonio Costa Diniz

Carlos Alberto Diniz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Diniz, Cláudio Machado"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.

Please choose a person to relate this publication to

Cláudio Walter

Cláudio Faria

Rogério Palhares Diniz

Roberto Antonio Costa Diniz

Carlos Alberto Diniz

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.