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Gate delay estimation in STA under dynamic power supply noise., , , , and . ASP-DAC, page 775-780. IEEE, (2010)A minimum decap allocation technique based on simultaneous switching for nanoscale SoC., and . CICC, page 21-24. IEEE, (2009)Power-Supply Noise Reduction with Design for Manufacturability., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3421-3428 (2005)Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement., , , , , , and . CICC, page 509-512. IEEE, (2004)A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2974-2982 (2003)Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits., , , , and . IEICE Trans. Electron., 88-C (4): 589-596 (2005)A substrate noise analysis methodology for large-scale mixed-signal ICs., , , , , , , , , and . CICC, page 369-372. IEEE, (2003)A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification., , , , , and . CICC, page 299-302. IEEE, (2002)LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator., , , and . ISQED, page 129-136. IEEE Computer Society, (2000)Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias., , , , , , and . CICC, page 35-38. IEEE, (2005)