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Disambiguation of "Matsutani, Hiroki"

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An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.

, , , , , and . FPT, page 163-170. IEEE, (2005)

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Hiroki Takahashi

Hiroki Kawamura

Hiroki Sumizawa

 

Other publications of authors with the same name

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips., , and . PDPTA, page 1343-1349. CSREA Press, (2005)LaKe: The Power of In-Network Computing., , and . ReConFig, page 1-8. IEEE, (2018)Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D"., , , and . NOCS, page 174-175. IEEE, (2014)MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories., , and . FPT, page 134-141. IEEE, (2018)Proxy Responses by FPGA-Based Switch for MapReduce Stragglers., , , and . IEICE Trans. Inf. Syst., 101-D (9): 2258-2268 (2018)A Hardware-Based Caching System on FPGA NIC for Blockchain., , , and . IEICE Trans. Inf. Syst., 101-D (5): 1350-1360 (2018)Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths., , , , , , and . PDP, page 143-147. IEEE, (2021)An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 105-A (3): 437-447 (2022)Accelerating ODE-Based Neural Networks on Low-Cost FPGAs., and . CoRR, (2020)A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs., , , and . CoRR, (2021)