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Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors., , , , , , and . SAC, page 1710-1716. ACM, (2016)Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding., , , and . ACM Trans. Embed. Comput. Syst., 9 (3): 22:1-22:26 (2010)Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism., , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2185-2200 (2020)I/O scheduling with mapping cache awareness for flash based storage systems., , , , and . EMSOFT, page 21:1-21:10. ACM, (2016)Introduction to the Special Issue on NVM and Storage., and . ACM Trans. Storage, 14 (1): 2:1-2:2 (2018)Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory., , , and . ISLPED, page 75-80. ACM, (2014)Sentinel Cells Enabled Fast Read for NAND Flash., , , , , and . HotStorage, USENIX Association, (2019)Accelerating General-purpose Lossless Compression via Simple and Scalable Parameterization., , , and . ACM Multimedia, page 3205-3213. ACM, (2022)Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors., , , , and . DAC, page 2:1-2:6. ACM, (2017)Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory., , , and . DAC, page 405-410. ACM, (2011)