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Optimization based on surrogate modeling for analog integrated circuits., , , , and . ICECS, page 9-12. IEEE, (2012)Automated cost function formulation for analog design optimization., , , and . ECCTD, page 559-562. IEEE, (2007)Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System., , , and . FDL, page 149-154. ECSI, Electronic Chips & Systems design Initiative, (2010)Hierarchical design flow for heterogenous systems using Pareto front interpolation., , and . ICECS, page 870-873. IEEE, (2014)Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts., , , , and . VLSI-SoC, page 281-286. IEEE, (2019)Reinforcement Learning for Analog Sizing Optimization., , , , , , , and . SMACD, page 1-4. IEEE, (2023)Artificial neural network-based solution for PSP MOSFET model card extraction., , , , , , , , and . VLSID, page 6-12. IEEE, (2024)CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder., , , and . DCIS, page 1-6. IEEE, (2018)Fast hierarchical system synthesis based on predictive models., , , and . NEWCAS, page 70-73. IEEE, (2020)3D-IC floorplanning: Applying meta-optimization to improve performance., , and . VLSI-SoC, page 404-409. IEEE, (2011)