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Analog Neural Networks With Deep-Submicrometer Nonlinear Synapses., , , , and . IEEE Micro, 39 (5): 55-63 (2019)Algorithm/Architecture Co-Design for Near-Memory Processing., , , , , , , and . ACM SIGOPS Oper. Syst. Rev., 52 (1): 109-122 (2018)The Mondrian Data Engine., , , , , , , and . ISCA, page 639-651. ACM, (2017)Highly Concurrent Latency-tolerant Register Files for GPUs., , , , , , , , , and . ACM Trans. Comput. Syst., 37 (1-4): 1:1-1:36 (2019)Scale-out Systolic Arrays., , , , , and . CoRR, (2022)MIAOW: An open source GPGPU., , , , , , , , , and . Hot Chips Symposium, page 1-43. IEEE, (2015)ColTraIn: Co-located DNN training and inference.. EPFL, Switzerland, (2020)Scale-out Systolic Arrays., , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 27:1-27:25 (June 2023)Training DNNs with Hybrid Block Floating Point., , , and . NeurIPS, page 451-461. (2018)Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation., , , , , , , , , and . CoRR, (2020)