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A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.

J. Tsai, H. Wang, Y. Yen, C. Lai, Y. Chen, P. Huang, P. Hsieh, H. Chen, and C. Lee. IEEE J. Solid State Circuits, 50 (6): 1382-1398 (2015)

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Cheng-Chieh Lee

Cheng-San Lee

Cheng-Yung Cheng

Hsi-Lin Chao

Kuo-Yih Chao

Other publications of authors with the same name

A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA.T. Chen, Y. Chiu, C. Wang, K. Chan, Y. Lin, M. Huang, C. Lu, W. Wang, C. Hu, C. Lee and 4 other author(s). IEEE J. Solid State Circuits, 42 (5): 983-991 (2007)An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter.W. Chou, T. Huang, Y. Lee, Y. Yang, Y. Su, K. Chen, C. Huang, Y. Lin, C. Lee, K. Wen and 3 other author(s). IEEE J. Solid State Circuits, 47 (7): 1568-1584 (2012)12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution.H. Yang, W. Yang, K. Chen, C. Wey, Y. Lin, C. Lee, J. Lin, T. Tsai, and S. Lai. ISSCC, page 230-231. IEEE, (2016)A low THD clock-free Class-D audio amplifier with an increased damping resistor and cross offset cancellation technique.Y. Chou, M. Chien, S. Chen, K. Chen, Y. Lin, T. Tsai, C. Huang, C. Lee, Z. Tai, Y. Cheng and 6 other author(s). ISCAS, page 2680-2683. IEEE, (2014)Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.W. Chen, T. Huang, T. Tsai, R. Peng, K. Lin, K. Chen, Y. Lin, T. Tsai, C. Huang, C. Lee and 5 other author(s). ESSCIRC, page 167-170. IEEE, (2014)Inductorless and electrolytic capacitorless pseudo-sine current controller in LED lighting system with 1.1W/2.2W power reduction.Y. Su, S. Chiu, C. Kuo, Y. Lee, K. Chen, Y. Lin, C. Huang, C. Lee, and Y. Chen. ESSCIRC, page 442-445. IEEE, (2012)Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors.M. Chien, W. Yang, Y. Chou, H. Chen, W. Chen, K. Chen, C. Wey, S. Lai, Y. Lin, C. Lee and 3 other author(s). ESSCIRC, page 188-191. IEEE, (2015)A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.Y. Lee, T. Huang, K. Chu, C. Chiu, K. Chen, Y. Lin, T. Tsai, C. Yeh, C. Huang, and C. Lee. ESSCIRC, page 161-164. IEEE, (2012)200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices.L. Chu, T. Yang, R. Huang, Y. Su, C. Lin, C. Wey, K. Chen, Y. Lin, C. Lee, J. Lin and 1 other author(s). A-SSCC, page 1-4. IEEE, (2015)A pseudo fixed switching frequency 2kHz/A in optimum on-time control buck converter with predicting correction technique for EMI solution.W. Chen, K. Lin, K. Chen, Y. Lin, T. Tsai, C. Huang, C. Lee, Z. Tai, Y. Cheng, C. Tsai and 4 other author(s). ISCAS, page 946-949. IEEE, (2014)

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Disambiguation of "Lee, Chao-Cheng"

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A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.

Please choose a person to relate this publication to

Cheng-Chieh Lee

Cheng-San Lee

Cheng-Yung Cheng

Hsi-Lin Chao

Kuo-Yih Chao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Chao-Cheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.

Please choose a person to relate this publication to

Cheng-Chieh Lee

Cheng-San Lee

Cheng-Yung Cheng

Hsi-Lin Chao

Kuo-Yih Chao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.