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Disambiguation of "Fornaciari, William"

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TEST: Assessing NoC Policies Facing Aging and Leakage Power.

, , , , and . DSD, page 606-613. IEEE Computer Society, (2015)

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William Pierson

William Herz

William Cahill

William Jorns

William Döhrmann

 

Other publications of authors with the same name

A sensor-less NBTI mitigation methodology for NoC architectures., and . SoCC, page 340-345. IEEE, (2012)A spice-based approach to steady state circuit analysis., and . I. J. Circuit Theory and Applications, 21 (5): 437-442 (1993)Fast system-level exploration of memory architectures driven by energy-delay metrics., , , and . ISCAS (4), page 502-505. IEEE, (2001)HANDS: heterogeneous architectures and networks-on-chip design and simulation., , and . ISLPED, page 261-266. ACM, (2012)Source-Level Models for Software Power Optimization., , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)An instruction-level functionally-based energy estimation model for 32-bits microprocessors., , , and . DAC, page 346-351. ACM, (2000)A new architecture for the automatic design of custom digital neural network., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (4): 502-506 (1995)Power estimation of embedded systems: a hardware/software codesign approach., , , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (2): 266-275 (1998)The role of VHDL within the TOSCA hardware/software codesign framework., , , and . EURO-DAC, page 612-617. IEEE Computer Society, (1994)Queueing Network Models for Performance Evaluation of ZigBee-Based WSNs., , , and . EPEW, volume 6342 of Lecture Notes in Computer Science, page 147-159. Springer, (2010)