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FaulTM: error detection and recovery using hardware transactional memory.

, , and . DATE, page 220-225. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories., , , , and . ISVLSI, page 149-154. IEEE Computer Society, (2015)Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm., , , , , and . PDP, page 184-191. IEEE Computer Society, (2016)CRC-Based Memory Reliability for Task-Parallel HPC Applications., , , , and . IPDPS, page 1101-1112. IEEE Computer Society, (2016)System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms., , , , , and . ESTIMedia, page 118-127. IEEE, (2014)Designing and Modelling Selective Replication for Fault-tolerant HPC Applications., , , , and . CCGrid, page 452-457. IEEE Computer Society / ACM, (2017)Circuit design of a novel adaptable and reliable L1 data cache., , , and . ACM Great Lakes Symposium on VLSI, page 333-334. ACM, (2013)Using Tag-Match Comparators for Detecting Soft Errors., and . IEEE Comput. Archit. Lett., 6 (2): 53-56 (2007)Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection., , , , and . ACM Trans. Archit. Code Optim., 11 (3): 32:1-32:24 (2014)A Runtime Heuristic to Selectively Replicate Tasks for Application-Specific Reliability Targets., , , , and . CLUSTER, page 498-505. IEEE Computer Society, (2016)ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers., , , , , , , , , and 3 other author(s). Microprocess. Microsystems, 39 (8): 1174-1189 (2015)