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The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.

, , , , and . IPDPS Workshops, page 700-707. IEEE, (2011)

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Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 52-66. Springer, (2006)LV*: A low complexity lazy versioning HTM infrastructure., , and . ICSAMOS, page 231-240. IEEE, (2010)A compiler algorithm that reduces read latency in ownership-based cache coherence protocols., and . PACT, page 69-78. IFIP Working Group on Algol / ACM, (1995)Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory., , , , and . PACT, page 203-204. IEEE Computer Society, (2011)Keynote talk: Towards automatic resource management in parallel architectures.. PACT, page 5. IEEE Computer Society, (2013)QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems., , and . IPDPS, page 303-313. IEEE, (2019)DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors., , , and . IPDPS, page 578-589. IEEE, (2020)Trends on heterogeneous and innovative hardware and software systems., , , , and . J. Parallel Distributed Comput., (2019)Introduction to the special issue on high-performance and embedded architectures and compilers., and . ACM Trans. Archit. Code Optim., 8 (4): 18:1-18:2 (2012)Panel Statement., , , , , , and . IPDPS, page 877. IEEE, (2011)