( en | de | ru )

 

Disambiguation of "López, Paula"

Author of the publication

copydeleteadd this publication to your clipboard
Design of multilayer discrete time cellular neural networks for image processing tasks based on genetic algorithms.

, , and . ISCAS, page 133-136. IEEE, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Margarita López López

Claudia Carolina López Yomayuza

Charakterisierung der Tollwutvakzinen Rabipur und Rabivac und der enthaltenen Virusstämme FluryLEP und PM 1503. Uni Gießen, (2009)

Fátima López López Pielow

Metamorfosis y metáfora: mito y discurso en Pedro Calderón de la Barca y Ovidio. Uni Wuppertal, (2008)

Caroline López

José Braulio López Padilla

 

Other publications of authors with the same name

Deep Learning-Based Multiple Object Visual Tracking on Embedded System for IoT and Mobile Edge Computing Applications., , , , and . CoRR, (2018)Efficient software-hardware 3D heat equation solver with applications on the non-destructive evaluation of minefields., , , and . Comput. Geosci., 35 (11): 2239-2249 (2009)Low-Power Techniques on a CMOS Vision Sensor Chip for Event Generation by Frame Differencing with High Dynamic Range., , , and . ICECS 2022, page 1-4. IEEE, (2022)1.88 nA Quiescent Current Capacitor-Less LDO with Adaptive Biasing Based on a SSF Absolute Voltage Difference Meter., , , , and . ISCAS, page 1-5. IEEE, (2020)HDC8192: A General Purpose Mixed-Signal CMOS Architecture for Massively Parallel Hyperdimensional Computing., , , , and . ISCAS, page 496-500. IEEE, (2022)Recent Advances in Computational Time-of-Flight Imaging., , , , and . ACSSC, page 1166-1173. IEEE, (2023)FPGA Finite-Difference Time-Domain solver for thermal simulation., , , and . FPL, page 721-722. IEEE, (2005)Live Demonstration: Light Energy Harvesting System with an On-Chip Solar Cell and Cold Start-Up., , , and . ISCAS, page 1-. IEEE, (2018)Performance analysis of high-speed MOS transistors with different layout styles., , , , and . ISCAS (4), page 3688-3691. IEEE, (2005)On-Chip Solar Energy Harvester and PMU With Cold Start-Up and Regulated Output Voltage for Biomedical Applications., , , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1103-1114 (2020)