Author of the publication

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.

, , , and . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)Instruction-based delay fault self-testing of pipelined processor cores., , , and . ISCAS (6), page 5686-5689. IEEE, (2005)Hypergraph Coloring and Reconfigured RAM Testing., and . IEEE Trans. Computers, 43 (6): 725-736 (1994)A Data Compression Technique for Built-In Self-Test., , and . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , and . IEEE Trans. Computers, 58 (5): 692-705 (2009)Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , and . DAC, page 527-532. IEEE, (2007)Analytic modeling of detection latency in mobile sensor networks., , and . IPSN, page 194-201. ACM, (2006)Modified T-Flip-Flop based scan cell for RAS., , , , and . European Test Symposium, page 113-118. IEEE Computer Society, (2010)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)