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Disambiguation of "Nandy, S. K."

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Low-Power Hierarchical Scan Test for Multiple Clock Domains.

, , and . J. Low Power Electron., 3 (1): 106-118 (2007)

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Constanze Nandy

Chong-hy S k

Han-gil S k

i-s k Pak

Sagnik Nandy

 

Other publications of authors with the same name

Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations., , and . J. Embed. Comput., 2 (1): 15-34 (2006)Synthesis of ASIPs for DSP algorithms., , and . Integr., 28 (1): 13-32 (1999)Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors., and . VLSI Design, 1 (2): 127-154 (1994)Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment.. VLSI Design, 1 (2): 155-167 (1994)On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications., , and . Int. J. Parallel Program., 31 (6): 469-487 (2003)On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation., , and . J. Syst. Archit., 54 (8): 797-815 (2008)Parallel Factorization of Boolean Polynomials., , , , , and . Ershov Informatics Conference, volume 11964 of Lecture Notes in Computer Science, page 80-94. Springer, (2019)A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design., , , , , , and . VLSID, page 64-69. IEEE, (2019)Applying Modified Householder Transform to Kalman Filter., , , , , , and . VLSID, page 431-436. IEEE, (2019)Hardware Solution for Real-Time Face Recognition., , , , , and . VLSID, page 81-86. IEEE Computer Society, (2015)