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Disambiguation of "Gu, Shouzhen"

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Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory.

, , , , and . ICCD, page 409-416. IEEE, (2020)

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Xuewu Gu

Xiaogang Gu

Wei Gu

Hyosong Gu

Jie Gu

 

Other publications of authors with the same name

Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs., , , , and . IEEE Trans. Parallel Distributed Syst., 26 (9): 2549-2560 (2015)Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint., , , , , and . J. Signal Process. Syst., 81 (3): 359-375 (2015)A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (12): 2008-2017 (2016)An efficient decoder for a linear distance quantum LDPC code., , and . CoRR, (2022)A space-based wear leveling for PCM-based embedded systems., , , , , and . RTCSA, page 145-148. IEEE Computer Society, (2013)Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory., , , , and . ICCD, page 409-416. IEEE, (2020)Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories., , , , and . J. Signal Process. Syst., 84 (1): 151-162 (2016)Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 2 (2): 129-142 (2016)Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories., , , , , and . IEEE Trans. Computers, 63 (8): 2039-2051 (2014)Hardware/Software Co-Exploration of Neural Architectures., , , , , , and . CoRR, (2019)