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Automated test bench generation for high-level synthesis flow ABELITE.

, , , , and . EWDTS, page 13-16. IEEE Computer Society, (2011)

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Structural Decision Diagrams in Digital Test - Theory and Applications, , , and . Springer, (2024)An External Test Approach for Network-on-a-Chip Switches., , and . ATS, page 437-442. IEEE, (2006)Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model., and . SBCCI, page 51-54. IEEE Computer Society, (1998)On automatic software-based self-test program generation based on high-level decision diagrams., , and . LATS, page 177. IEEE, (2016)Test Generation for Digital Systems Based on Alternative Graphs.. EDCC, volume 852 of Lecture Notes in Computer Science, page 151-164. Springer, (1994)Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation., , and . ISCAS, page 1-5. IEEE, (2018)Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells., , and . DDECS, page 21-26. IEEE, (2018)Laboratory framework TEAM for investigating the dependability issues of microprocessor systems., , , and . EWME, page 80-83. IEEE, (2014)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE Computer Society, (2010)