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Disambiguation of "Huang, Haimeng"

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SiC trench MOSFET with integrated side-wall Schottky barrier diode having P+ electric field shield.

, , , , , and . IEICE Electron. Express, 16 (5): 20181135 (2019)

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Josef Huang

Pa Huang

Zheng Huang

Yuejun Huang

Shiwei Huang

 

Other publications of authors with the same name

Analytical Models of Breakdown Voltage and Specific On-Resistance for Vertical GaN Unipolar Devices., , , , and . IEEE Access, (2019)Temperature Dependent Optimization for Specific On-Resistance for 900 V Superjunction MOSFETs: Numerical Calculation and Comparison., , , , , , , , , and . ASICON, page 1-4. IEEE, (2023)A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances., , , , , , , and . ASICON, page 1-4. IEEE, (2021)Modeling and simulation of an insulated-gate HEMT using p-SnO2 gate for high VTH design., , , , , , and . Microelectron. J., (September 2023)Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer., , , , , and . IEICE Electron. Express, 17 (2): 20190673 (2020)SiC trench MOSFET with integrated side-wall Schottky barrier diode having P+ electric field shield., , , , , and . IEICE Electron. Express, 16 (5): 20181135 (2019)An analytical model for SOI triple RESURF devices., , and . ASICON, page 547-550. IEEE, (2011)Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction., , , , , , , and . ASICON, page 1-4. IEEE, (2023)A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron, sp., , , , , and . ASICON, page 1-4. IEEE, (2021)