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An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.

S. Yonar, P. Francese, M. Brändli, M. Kossel, T. Morf, J. Proesel, S. Rylov, H. Ainspan, M. Cochet, Z. Deniz, T. Dickson, T. Beukema, C. Baks, M. Beakes, J. Bulzacchelli, Y. Choi, B. Yoo, H. Ahn, D. Lim, G. Kang, S. Park, M. Meghelli, H. Rhew, D. Friedman, M. Choi, M. Soyuer, and J. Shin. VLSI Technology and Circuits, page 168-169. IEEE, (2022)

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Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Manfred Herschel

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A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.T. Dickson, Y. Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, and D. Friedman. CICC, page 1-4. IEEE, (2015)An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.T. Dickson, Y. Liu, S. Rylov, B. Dang, C. Tsang, P. Andry, J. Bulzacchelli, H. Ainspan, X. Gu, L. Turlapati and 4 other author(s). IEEE J. Solid State Circuits, 47 (4): 884-896 (2012)RF circuit design aspects of spiral inductors on silicon.J. Burghartz, D. Edelstein, M. Soyuer, H. Ainspan, and K. Jenkins. IEEE J. Solid State Circuits, 33 (12): 2028-2034 (1998)A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.T. Beukema, M. Sorna, K. Selander, S. Zier, B. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker and 1 other author(s). IEEE J. Solid State Circuits, 40 (12): 2633-2645 (2005)An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator.M. Soyuer, J. Burghartz, H. Ainspan, K. Jenkins, P. Xiao, A. Shahani, M. Dolan, and D. Harame. IEEE J. Solid State Circuits, 32 (9): 1451-1454 (1997)FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.B. Lee, N. Dupuis, J. Orcutt, J. Ayala, K. Nummy, H. Ainspan, J. Proesel, C. Baks, D. Gill, M. Meghelli and 1 other author(s). OFC, page 1-3. IEEE, (2018)A 5.2 GHz 3.3 V I/Q SiGe RF transceiver.J. Plouchart, H. Ainspan, and M. Soyuer. CICC, page 217-220. IEEE, (1999)Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.T. Dickson, Z. Deniz, M. Cochet, J. Bulzacchelli, M. Kessel, P. Francese, T. Morf, J. Proesel, H. Ainspan, M. Brändli and 1 other author(s). CICC, page 1-8. IEEE, (2024)TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.D. Bhattacharya, R. Joshi, H. Ainspan, N. Sathaye, M. Bajaj, S. Gundapaneni, and N. Jha. CICC, page 1-4. IEEE, (2014)Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier.D. Kuchta, H. Ainspan, F. Canora, and R. Jr.. IBM J. Res. Dev., 39 (1-2): 63-72 (1995)

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Disambiguation of "Ainspan, Herschel A."

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An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.

Please choose a person to relate this publication to

Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Manfred Herschel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ainspan, Herschel A."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.

Please choose a person to relate this publication to

Andreas Herschel

Olga Herschel

Wilhelm Herschel

Knut Herschel

Manfred Herschel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.