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Disambiguation of "Wei, Kaijie"

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An implementation methodology for Neural Network on a Low-end FPGA Board.

, , and . CANDAR, page 228-234. IEEE, (2020)

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Kaijie Zhou

Wei Wei

Wei Wei

Wei Wei

Wei Wei

 

Other publications of authors with the same name

An implementation methodology for Neural Network on a Low-end FPGA Board., , and . CANDAR, page 228-234. IEEE, (2020)RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA., , , and . HEART, page 1-9. ACM, (2022)Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA., , , , and . Int. J. Netw. Comput., 12 (2): 425-445 (2022)RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability., , , and . IEICE Trans. Inf. Syst., 106 (3): 337-348 (March 2023)Weight Least Square Filter for Improving the Quality of Depth Map on FPGA., , , , and . CANDAR (Workshops), page 297-300. IEEE, (2021)FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board., , and . MCSoC, page 53-60. IEEE, (2019)A cost/power efficient storage system with directly connected FPGA and SATA disks., , , , and . MCSoC, page 51-58. IEEE, (2023)Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board., , , and . COOL CHIPS, page 1-6. IEEE, (2023)An implementation methodology for Neural Network on a Low-end FPGA Board., , and . Int. J. Netw. Comput., 11 (2): 172-197 (2021)CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis., , , and . IEICE Trans. Inf. Syst., 104-D (12): 2048-2056 (2021)