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A low power fault secure timer implementation based on the Gray encoding scheme., , , and . ICECS, page 537-540. IEEE, (2002)Implementation of HSSec: a high-speed cryptographic co-processor., , , and . ETFA, page 625-631. IEEE, (2007)Throughput Optimization of the Cipher Message Authentication Code., , , and . DSP, page 495-498. IEEE, (2007)Prototype Haptic Feedback Device for Robot-Assisted Minimally Invasive Surgery., and . SEEDA-CECNSM, page 1-6. IEEE, (2021)Cipher Block Based Authentication Module: a Hardware Design Perspective., , , , and . J. Circuits Syst. Comput., 20 (2): 163-184 (2011)Design of low-power on-line reconfigurable datapaths using self-checking circuits., , and . ICECS, page 1565-1568. IEEE, (2001)Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core., , , , , and . ICECS, page 1180-1183. IEEE, (2006)Cybersecurity and Democracy: A Review., and . SEEDA-CECNSM, page 1-8. IEEE, (2023)Low-Power Electroencephalographic Data Encoding System for Implantable Brain Stimulation Systems., , and . SEEDA-CECNSM, page 1-5. IEEE, (2021)High-throughput ASIC implementation of an encryption core for securing shared storage media., , and . DSP, page 1-5. IEEE, (2011)