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Improving approximate-TMR using multi-objective optimization genetic algorithm., , , , , , and . LATS, page 1-6. IEEE, (2018)From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 520-532 (2020)Application and Product-Volume-Specific Customization of BEOL Metal Pitch., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1627-1636 (2018)Logic IP for Low-Cost IC Design in Advanced CMOS Nodes., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 585-595 (2020)Synthesis of threshold logic gates to nanoelectronics., , , and . SBCCI, page 1-6. IEEE, (2013)Functional composition: A new paradigm for performing logic synthesis., , and . ISQED, page 236-242. IEEE, (2012)Improved logic synthesis for memristive stateful logic using multi-memristor implication., , , , and . ISCAS, page 181-184. IEEE, (2015)Methodology for achieving best trade-off of area and fault masking coverage in ATMR., , , , , and . LATW, page 1-6. IEEE, (2014)Exploring the use of approximate TMR to mask transient faults in logic with low area overhead., , , and . Microelectron. Reliab., 55 (9-10): 2072-2076 (2015)A Simple and Effective Heuristic Method for Threshold Logic Identification., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (5): 1023-1036 (2018)