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Disambiguation of "Hwang, Kyu-Dong"

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A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer.

, , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Suk-Kyu Hwang

Dong-Kyu Kang

Dong Kyu Kim

Dong Kyu Lee

Choy Kyungcheol

 

Other publications of authors with the same name

A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface., and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 3016-3024 (2014)A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer., , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer., , , , , and . ISSCC, page 128-130. IEEE, (2011)A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping., , , and . ISCAS, page 1300-1303. IEEE, (2010)A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications., , , , , , , , , and 11 other author(s). ISSCC, page 210-212. IEEE, (2018)A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer., , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3083-3093 (2022)A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer., , , , , and . IEEE Trans. Circuits Syst. Video Techn., 22 (4): 589-604 (2012)An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages., and . ISCAS, page 3973-3976. IEEE, (2010)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (6): 302-306 (2013)