( en | de | ru )

 

Disambiguation of "Kim, Hyun-Jin"

Author of the publication

copydeleteadd this publication to your clipboard
Android Malware Detection Based on Useful API Calls and Machine Learning.

, , , , , , and . AIKE, page 175-178. IEEE Computer Society, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jin Hyun Kim

Hyun-Jin Kim

Hyun-Jin Kim

Jin Kim

Jin Kim

 

Other publications of authors with the same name

Construction of extremal self-dual codes over F2+uF2 with an automorphism of odd order., and . Finite Fields Their Appl., 18 (5): 971-992 (2012)A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling., , , , , , and . IEEE J. Solid State Circuits, 40 (1): 89-101 (2005)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)Genome sequence of the hot pepper provides insights into the evolution of pungency in Capsicum species, , , , , , , , , and 61 other author(s). Nat. Genet., (2014)A formal modeling and analysis framework for software product line of preemptive real-time systems., , , , and . SAC, page 1562-1565. ACM, (2016)Efficient Android Malware Detection Using API Rank and Machine Learning., , , , and . J. Internet Serv. Inf. Secur., 9 (1): 48-59 (2019)PLAM: A Posit Logarithm-Approximate Multiplier., , , , , and . IEEE Trans. Emerg. Top. Comput., 10 (4): 2079-2085 (2022)Towards Overhead-Free Interface Theory for Compositional Hierarchical Real-Time Systems., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2869-2880 (2018)Supporting Virtualization Standard for Network Devices in RTEMS Real-Time Operating System., , and . EWiLi, volume 1464 of CEUR Workshop Proceedings, CEUR-WS.org, (2015)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)