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Disambiguation of "Maestro, Juan Antonio"

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New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.

, , , and . Des. Autom. Embed. Syst., 9 (3): 193-210 (2004)

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Juan Antonio Estada

Juan Antonio Monroy

Juan Antonio Ennis

Juan Antonio Pajarin Rodriguez

Juan Antonio Diaz Gonzalez

 

Other publications of authors with the same name

Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study., , , and . J. Signal Process. Syst., 52 (3): 231-247 (2008)Protection Scheme for Star Tracker Images., , , and . IEEE Trans. Aerosp. Electron. Syst., 55 (1): 486-492 (2019)Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA., , , and . Circuits Syst. Signal Process., 39 (11): 5529-5542 (2020)Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput., , and . IEEE Trans. Computers, 65 (1): 326-331 (2016)Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes., , and . IEEE Trans. Computers, 65 (9): 2932-2938 (2016)Low Complexity Concurrent Error Detection for Complex Multiplication., , , and . IEEE Trans. Computers, 62 (9): 1899-1903 (2013)On the expected longest length probe sequence for hashing with separate chaining., , and . J. Discrete Algorithms, 9 (3): 307-312 (2011)Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016)., , , , and . Microelectron. Reliab., (2017)Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (11): 1933-1943 (2016)A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection., , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (3): 376-380 (2018)