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Optimization of the PLL based TRNG design using the genetic algorithm., , , and . ISCAS, page 1-4. IEEE, (2017)Transient Effect Ring Oscillators Leak Too., , , , and . ISVLSI, page 37-42. IEEE, (2019)A comprehensive hardware/software infrastructure for IP cores design protection., , , and . FPT, page 263-266. IEEE, (2017)Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs., , , , and . IVSW, page 146-151. IEEE, (2017)An Evaluation Procedure for Comparing Clock Jitter Measurement Methods., , , , and . CARDIS, volume 13820 of Lecture Notes in Computer Science, page 167-187. Springer, (2022)Complete activation scheme for FPGA-oriented IP cores design protection., , , , , and . FPL, page 1. IEEE, (2017)A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices., , , , and . FPL, page 1-10. IEEE, (2016)Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (1): 97-109 (2018)Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2560-2571 (2019)