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Disambiguation of "Ahn, Minwook"

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Source level offloading for special-purpose hardware accelerators.

, , , and . ICCE, page 532-533. IEEE, (2015)

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Jochen Ahn

Rolf Ahn

Stephan Ahn

Hyewon Ahn

John Ahn

 

Other publications of authors with the same name

Two versions of architectures for dynamic implied addressing mode., , , , and . J. Syst. Archit., 56 (8): 368-383 (2010)Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation., , and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 151-166. Springer, (2003)Nop compression scheme for high speed DSPs based on VLIW architecture., , , , , , and . ICCE, page 304-305. IEEE, (2014)Optimistic coalescing for heterogeneous register architectures., , and . LCTES, page 93-102. ACM, (2007)Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers., and . Trans. High Perform. Embed. Archit. Compil., (2009)Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode., , , , and . HPCC, page 545-550. IEEE, (2009)Iterative Algorithm for Compound Instruction Selection with Register Coalescing., , , , and . DSD, page 513-520. IEEE Computer Society, (2009)Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os., , , , , , and . ICCAD, page 747-754. IEEE, (2013)Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set., , , , and . IPDPS, page 119-130. IEEE Computer Society, (2012)A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (11): 1565-1578 (2009)