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Disambiguation of "Mak, Pui-In"

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28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays.

, , , , , and . ISSCC, page 474-475. IEEE, (2016)

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Ellen Mak

Beatrice Puiu

Rebecca Mak

Kwok Mak

Ale PuÌ

 

Other publications of authors with the same name

A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays., , , , , and . IEEE J. Solid State Circuits, 52 (1): 284-297 (2017)A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop., , and . IEEE J. Solid State Circuits, 52 (8): 2055-2070 (2017)A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8-µW Steady-State Power., , , and . IEEE J. Solid State Circuits, 53 (9): 2624-2635 (2018)Correction to Ä 0.016 mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW"., , , and . IEEE J. Solid State Circuits, 48 (6): 1539 (2013)A µNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet., , , and . IEEE J. Solid State Circuits, 51 (10): 2274-2286 (2016)An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF., , and . IEEE J. Solid State Circuits, 49 (11): 2547-2559 (2014)Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters., , , and . IEEE J. Solid State Circuits, 53 (12): 3455-3469 (2018)A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS., and . IEEE J. Solid State Circuits, 46 (9): 1970-1984 (2011)A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2889-2902 (2018)A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 3014-3026 (2018)