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Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (2): 228-243 (1996)Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 608-619 (1998)Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression., , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 17-23 (2010)Warehouse-scale video acceleration: co-design and deployment in the wild., , , , , , , , , and 42 other author(s). ASPLOS, page 600-615. ACM, (2021)Synthesis of Sequential Circuits for Robust Path Delay Fault Testability., and . VLSI Design, page 275-280. IEEE Computer Society, (1993)A structured test re-use methodology for core-based system chips., and . ITC, page 294-302. IEEE Computer Society, (1998)Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches., and . ICCD, page 91-96. IEEE Computer Society, (1994)Genesis: A Behavioral Synthesis System for Hierarchical Testability., and . EDAC-ETC-EUROASIC, page 272-276. IEEE Computer Society, (1994)A Unifying Methodology for Intellectual Property and Custom Logic Testing., , and . ITC, page 639-648. IEEE Computer Society, (1996)Test Compaction by Using Linear-Matrix Driven Scan Chains.. DFT, page 185-190. IEEE Computer Society, (2003)