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Disambiguation of "Vuillod, Patrick"

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Clock skew optimization for peak current reduction.

, , , and . ISLPED, page 265-270. IEEE, (1996)

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Patrick Pfeffer

Optimiertes Design kombinatorischer Verbindungsbibliotheken durch genetische Algorithmen und deren Bewertung anhand wissensbasierter Protein-Ligand-Bindungsprofile. Uni Marburg, (2009)

Patrick Hansen

Entwicklung eines energetischen Sanierungsmodells für den europäischen Wohngebäudesektor unter dem Aspekt der Erstellung von Szenarien für Energie- und Co_1tn2-Einsparpotenziale bis 2030. Uni Siegen, (2009)

Ekkehard Patrick

Patrick Fleischmann

Patrick Horster

 

Other publications of authors with the same name

Scalable Boolean Methods in a Modern Synthesis Flow., , , , , , , , and . DATE, page 1643-1648. IEEE, (2019)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , and . DAC, page 1-6. IEEE, (2020)Improvements to boolean resynthesis., , , , , , , and . DATE, page 755-760. IEEE, (2018)Integrated ESOP Refactoring for Industrial Designs., , , , , and . ICECS, page 369-372. IEEE, (2018)Clock Skew Optimization for Peak Current Reduction., , , and . VLSI Signal Processing, 16 (2-3): 117-130 (1997)Clock skew optimization for peak current reduction., , , and . ISLPED, page 265-270. IEEE, (1996)Generalized matching from theory to application., , and . ICCAD, page 13-20. IEEE Computer Society / ACM, (1997)Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification., , , and . ISSS, page 57-. ACM / IEEE Computer Society, (1996)Iterative remapping for logic circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (10): 948-964 (1998)Logic optimization and synthesis: Trends and directions in industry., , , and . DATE, page 1303-1305. IEEE, (2017)