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An efficient interpolation filter VLSI architecture for HEVC standard., , , and . ChinaSIP, page 384-388. IEEE, (2014)A low power lossy frame memory recompression algorithm., , , , and . APSIPA, page 1-4. IEEE, (2016)A CNN-based Coding Unit Partition in HEVC for Video Processing., , , and . RCAR, page 273-276. IEEE, (2019)Towards seamless localization in challenging environments via high-definition maps and multi-sensor fusions., , and . IV, page 933-940. IEEE, (2024)6D Robotic Assembly Based on RGB-only Object Pose Estimation., , , and . IROS, page 4736-4742. IEEE, (2022)A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC., , , , and . PCM (1), volume 9916 of Lecture Notes in Computer Science, page 469-478. Springer, (2016)A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks., , , , , , and . GlobalSIP, page 1-5. IEEE, (2019)An efficient interpolation filter VLSI architecture for HEVC standard., , , , and . EURASIP J. Adv. Signal Process., (2015)Pixel-grain prediction and K-order UEG-rice entropy coding oriented lossless frame memory compression for motion estimation in HEVC., , , and . ICIP, page 1995-1999. IEEE, (2015)An efficient interpolation filter VLSI architecture for HEVC., , and . ICASSP, page 1106-1110. IEEE, (2015)