( en | de | ru )

 

Disambiguation of "Lerner, Scott"

Author of the publication

copydeleteadd this publication to your clipboard
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation.

, , , and . VLSID, page 135-140. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hermann Lerner

Martina Christine Scotti

Pierre-François Scotto

Peter Scott

Willibald Lerner

 

Other publications of authors with the same name

NoC Router Lifetime Improvement using Per-Port Router Utilization., , and . ISCAS, page 1-5. IEEE, (2018)Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 700-710 (2019)Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors., and . ISQED, page 379-384. IEEE, (2017)Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement., , , , and . ISCAS, page 1-5. IEEE, (2018)Stability of Rotary Traveling Wave Oscillators under process variations and NBTI., , , and . ISCAS, page 1-4. IEEE, (2017)Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1636-1645 (2021)Robust Low Power Clock Synchronization for Multi-Die Systems., , , , and . ISLPED, page 1-6. IEEE, (2019)Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 1-10 (2019)WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS., and . ISVLSI, page 465-470. IEEE Computer Society, (2017)Slew-down: analysis of slew relaxation for low-impact clock buffers., , and . SLIP, page 1-4. IEEE Computer Society, (2017)